Verification register Energy, Climate, Space & Materials
Current reading
The readiness gap, in one scan
AI-assisted assembly · derived results
- Claimed
- 25
- Reported
- 21
- Verified
- 19
- Gap
- +6
Public ambition and stated capability
Observed practitioner reporting
Independently supported evidence
Claimed minus verified
Evidence strength Strong
Decision
What the current evidence supports
Human editorial judgment · 2026-06-28
Too early to adopt
- Why
- A landmark lab milestone (largest 2D logic chip to date) but at ~1 kHz / 4 V / n-type-only it is a scientific proof, not an engineering substrate; authors and trade press agree there is no commercial path within the relevant horizon.
- Next
- Track follow-on papers for CMOS (n+p) 2D integration and any move to industrial fabs; revisit if clock crosses ~MHz with maintained yield.
Constraints
Blockers
No named blocker is present in the current public projection.
Evidence summary
Derived counts
AI-assisted assembly
- Total
- 7
- Tier 1
- 0
- Tier 2
- 4
- Tier 3
- 3
- Supports
- 2
- Contradicts
- 3
- Context
- 2
- Latest observed
- 2025-04-18
Counts and dates only. Raw signals, private excerpts, trust records, and internal corpus material are not published here.
Publication record
Revisions
Initial public reading
This is the initial public reading. No earlier readiness change is recorded.