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Verification register Energy, Climate, Space & Materials

Readiness verdict

WUJI RV32 2D-Semiconductor RISC-V Microprocessor

A dated reading of what is claimed, reported, and independently verified in the current evidence.

As of
2026-08-20
Revision
1
Method
v1.3.0

Current reading

Readiness band and full integer triple

AI-assisted assembly · derived results

Readiness band

Emerging

Primary summary from verified readiness

Confidence
71% · stale
Computed at
2026-08-20T10:54:16.279273+00:00
Claimed
25

Public ambition and stated capability

Reported
21

Observed practitioner reporting

Verified
19

Independently supported evidence

Gap
+6

Claimed leads verified

Evidence strength Strong

Decision

What the current evidence supports

Human editorial judgment · 2026-08-20

Too early to adopt

Why
A landmark lab milestone (largest 2D logic chip to date) but at ~1 kHz / 4 V / n-type-only it is a scientific proof, not an engineering substrate; authors and trade press agree there is no commercial path within the relevant horizon.
Next
Track follow-on papers for CMOS (n+p) 2D integration and any move to industrial fabs; revisit if clock crosses ~MHz with maintained yield.

Constraints

Blockers

No named blocker is present in the current public projection.

Evidence summary

Derived counts

AI-assisted assembly

Total
11
Tier 1
0
Tier 2
7
Tier 3
4
Supports
4
Contradicts
4
Context
3
Latest observed
2025-04-18

Counts and dates only. Raw signals, private excerpts, trust records, and internal corpus material are not published here.

Publication record

Revisions

Initial public reading

  1. 2026-07-19 Reading moved from emerging to emerging.

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