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Verification register Frontier Hardware & Quantum

Readiness verdict

STMicroelectronics Gen5 STPOWER SiC

A dated reading of what is claimed, reported, and independently verified in the current evidence.

As of
2026-06-28
Revision
1
Method
v1.0.0

Current reading

The readiness gap, in one scan

AI-assisted assembly · derived results

Claimed
35

Public ambition and stated capability

Reported
25

Observed practitioner reporting

Verified
17

Independently supported evidence

Gap
+18

Claimed minus verified

Evidence strength Growing

Decision

What the current evidence supports

Human editorial judgment · 2026-06-28

Wait for stronger evidence

Why
Gen5 is a credibly-announced planar high-density architecture but is pre-spec and pre-sample with zero quantified data and a ~2027 horizon; committing now would be betting on roadmap promises
Next
Track ST's SiC roadmap milestones (incl. Catania vertically-integrated substrate fab ramping 2026); design current platforms around shipping Gen4 (750V/1200V) and re-evaluate Gen5 only when a datasheet with numeric RDS(on)/FOM and samples appear

Constraints

Blockers

No named blocker is present in the current public projection.

Evidence summary

Derived counts

AI-assisted assembly

Total
6
Tier 1
0
Tier 2
6
Tier 3
0
Supports
2
Contradicts
3
Context
1
Latest observed
2024-09-26

Counts and dates only. Raw signals, private excerpts, trust records, and internal corpus material are not published here.

Publication record

Revisions

Initial public reading

This is the initial public reading. No earlier readiness change is recorded.

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