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Verification register Frontier Hardware & Quantum

Readiness verdict

STMicroelectronics Gen5 STPOWER SiC

A dated reading of what is claimed, reported, and independently verified in the current evidence.

As of
2026-08-20
Revision
1
Method
v1.3.0

Current reading

Readiness band and full integer triple

AI-assisted assembly · derived results

Readiness band

Emerging

Primary summary from verified readiness

Confidence
67% · stale
Computed at
2026-08-20T10:52:14.405351+00:00
Claimed
35

Public ambition and stated capability

Reported
25

Observed practitioner reporting

Verified
17

Independently supported evidence

Gap
+18

Claimed leads verified

Evidence strength Growing

Decision

What the current evidence supports

Human editorial judgment · 2026-08-20

Wait for stronger evidence

Why
Gen5 is a credibly-announced planar high-density architecture but is pre-spec and pre-sample with zero quantified data and a ~2027 horizon; committing now would be betting on roadmap promises
Next
Track ST's SiC roadmap milestones (incl. Catania vertically-integrated substrate fab ramping 2026); design current platforms around shipping Gen4 (750V/1200V) and re-evaluate Gen5 only when a datasheet with numeric RDS(on)/FOM and samples appear

Constraints

Blockers

No named blocker is present in the current public projection.

Evidence summary

Derived counts

AI-assisted assembly

Total
7
Tier 1
0
Tier 2
7
Tier 3
0
Supports
3
Contradicts
3
Context
1
Latest observed
2024-09-26

Counts and dates only. Raw signals, private excerpts, trust records, and internal corpus material are not published here.

Publication record

Revisions

Initial public reading

  1. 2026-07-19 Reading moved from emerging to emerging.

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