Intel TDX Connect

A dated reading of what is claimed, reported, and independently verified in the current evidence.

Current reading

The readiness gap, in one scan

AI-assisted assembly · derived results

Evidence strength Strong

Decision

Human editorial judgment · 2026-06-28

Track; not yet

Why: The standards-based architecture is sound and Xeon 6 silicon ships, but the full stack (host OS, hypervisor, device firmware, kernel attestation) is pre-GA; only base Intel TDX (CPU-only) CVMs are GA today, and the GPU pairing is shipping on the AMD path, not Intel's.
Next: Track the GA Azure confidential-GPU path (AMD SEV-SNP + NVIDIA H100, NCC H100 v5) as the practical on-ramp for confidential AI today; revisit Intel TDX Connect when device attestation lands in mainline Linux past Phase 1 and a GA cloud SKU pairing Intel TDX with an attested GPU appears (target 2026).

Constraints

No named blocker is present in the current public projection.

Evidence summary

AI-assisted assembly

Counts and dates only. Raw signals, private excerpts, trust records, and internal corpus material are not published here.

Publication record

Initial public reading

This is the initial public reading. No earlier readiness change is recorded.