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Verification register Frontier Hardware & Quantum

Readiness verdict

Ambiq Atomiq NPU SoC

A dated reading of what is claimed, reported, and independently verified in the current evidence.

As of
2026-06-28
Revision
1
Method
v1.0.0

Current reading

The readiness gap, in one scan

AI-assisted assembly · derived results

Claimed
35

Public ambition and stated capability

Reported
35

Observed practitioner reporting

Verified
31

Independently supported evidence

Gap
+4

Claimed minus verified

Evidence strength Growing

Decision

What the current evidence supports

Human editorial judgment · 2026-06-28

Track; not yet

Why
The value proposition (300 mV subthreshold operation on TSMC N12e FinFET with an Ethos-U85 NPU) is compelling, but the part is pre-silicon with a confirmed 2027 production target and entirely vendor-claimed performance, so adoption decisions should wait for measured data.
Next
Add Atomiq110 to a watchlist and revisit once first silicon samples and independent power/perf benchmarks exist; the March 2026 Embedded World 12nm SPOT disclosure has already landed, so the next real checkpoint is sample availability ahead of 2027 production.

Constraints

Blockers

No named blocker is present in the current public projection.

Evidence summary

Derived counts

AI-assisted assembly

Total
5
Tier 1
2
Tier 2
2
Tier 3
1
Supports
3
Contradicts
1
Context
1
Latest observed
2026-03-05

Counts and dates only. Raw signals, private excerpts, trust records, and internal corpus material are not published here.

Publication record

Revisions

Initial public reading

This is the initial public reading. No earlier readiness change is recorded.

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